NUCA Caches: Analysis of Performance Sensitivity to NoC Parameters
نویسندگان
چکیده
The on-chip network (NoC) is a fundamental component of Non Uniform Cache Architectures and may significantly affect the performance of the overall system. The analysis described in this work evaluates the performance sensitivity of a single processor system adopting a NUCA L2 cache with respect to some NoC parameters, namely the hop latency and the buffering capacity of routers. The results show that the performance sensitivity to the hop latency is very high, thus suggesting that multi-cycle router architectures are not adequate, while the network traffic imposes a moderate load on the buffering resources.
منابع مشابه
Reducing Sensitivity to NoC Latency in NUCA Caches
Non Uniform Cache Architectures (NUCA) are a novel design paradigm for large last-level on-chip caches which have been introduced to deliver low access latencies in wire-delay dominated environments. Typically, NUCA caches make use of a network-on-chip (NoC) to connect the different sub-banks and the cache controller. This work analyzes how different network parameters, namely hop latency and b...
متن کاملOn-Chip Networks: Impact on the Performance of NUCA Caches
Non Uniform Cache Architectures (NUCA) are a new design paradigm for large last-level on-chip caches and have been introduced to deliver low access latencies in wire-delay dominated environments. Their structure is partitioned into sub-banks and the resulting access latency is a function of the physical position of the requested data. Typically, NUCA caches make use of a switched network to con...
متن کامل3D Tree Cache – A Novel Approach to Non- Uniform Access Latency Cache Architectures for 3D CMPs
We consider a non-uniform access latency cache architecture (NUCA) design for 3D chip multiprocessors (CMPs) where cache structures are divided into small banks interconnected by a network-on-chip (NoC). In earlier NUCA designs, data is placed in banks either statically (S-NUCA) or dynamically (D-NUCA). In both SNUCA and D-NUCA designs, scaling to hundreds of cores can pose several challenges. ...
متن کاملImpact of on-chip network parameters on nuca cache performances
Non-uniform cache architectures (NUCAs) are a novel design paradigm for large last-level on-chip caches, which have been introduced to deliver low access latencies in wire-delay-dominated environments. Their structure is partitioned into sub-banks and the resulting access latency is a function of the physical position of the requested data. Typically, NUCA caches employ a switched network, made...
متن کاملTask Scheduling for Many-Cores with S-NUCA Caches
A many-core processor may comprise a large number of processing cores on a single chip. The many-core’s last-level shared cache can potentially be physically distributed alongside the cores in the form of cache banks connected through a Network on Chip (NoC). Static Non-Uniform Cache Access (SNUCA) memory address mapping policy provides a scalable mechanism for providing the cores quick access ...
متن کامل